1. Field of the invention
This invention relates to a method of chamfering a semiconductor wafer, and more particularly to a method of chamfering a semiconductor wafer, wherein a rotating grindstone is abutted against the peripheral edge of the rotating semiconductor wafer for grinding the peripheral edge of the semiconductor wafer.
2. Description of the Related Art
In the semiconductor wafer cut by slicing, the surface thereof is subjected to lapping and the peripheral edge thereof is chamfered to prevent cracking of the wafer and to prevent dust from adhering to the wafer. That is, as shown in FIG. 9, an inclined surface 14 of a rotating grindstone 12 with a groove is urged against a rotating semiconductor wafer 10 to chamfer the peripheral edges 16 and 17 of the semiconductor wafer.
However, according to the conventional method of chamfering the semiconductor wafer, as shown in FIG. 9, the moving direction A of an abrasive grain 15 is limited to the circumferential direction of the wafer, whereby a streak A' is formed on a chamfered surface by the abrasive grain (partial cutting edge), so that the surface roughness accuracy of the chamfered surface is not satisfactory. When the surface roughness accuracy of the chamfered surface is unsatisfactory, the dust adheres to the peripheral edge surface where chips due to partial cracks on the peripheral edge surface of the wafer are formed. Further, there is a factor of producing the dust due to crouching of fine particles between the cracks, so that an adverse influence is rendered to the post-treatment process of the wafer. In order to obviate this drawback, the count number of the grindstone is raised, the cut-in amount is decreased, the number of times of dressing is increased and several grindstones are exchanged (at two stages, three stages and so forth) to raise the surface roughness accuracy of the ground surface, however, these counter measures present a disadvantage of lowering the grinding efficiency.